A Novel Diagonal Hamming technique for efficient Multi-Bit error correction in Memories

Authors

  • T. Vasudeva Reddy Department of ECE, B V Raju Institute of Technology, Narsapur, Medak dt, Telangana, India Author
  • V. Srilatha Reddy Department of EIE, CVR College of Engineering, Telangana, India Author
  • Papani Srinivas Department of ECE, Vignan Institute of Technology and Science, Deshmukhi, Telangana, India Author
  • K. Madhava Rao Department of ECE, B V Raju Institute of Technology, Narsapur, Medak dt, Telangana, India Author
  • T. Prem chander Department of CSE, Matrusri Engineering College, Saidabad, Hyderabad, Telangana, India Author
  • M. S. S. Bhargav Department of ECE, B V Raju Institute of Technology, Narsapur, Medak dt, Telangana, India Author

Abstract

This research articles represents the On-chip memory in a die that is prone bit errors that resulting in single upset units to multiple upset units. Some of these errors are caused by environmental factors, alpha particles, cosmic rays and extreme temperatures such instances can lead to data corruption, creates critical issue especially in space application. To address such issue, this article presents an enhanced error detection and detection techniques. The proposed models describes the utilization of code based on divide symbol scheme, specially introduced radiation introduced in memory devices. The core of this technique involves a series of XOR operations to encode data bits, diagonal bits, and parity and check bits. To retrieve the original data, a second XOR operation is performed between the encoded bits and recalculated encoded bits. Following this, a verification, selection, and correction process is initiated. The proposed method focuses on detecting and correcting soft errors, which are temporary data corruption events caused by voltage fluctuations or external radiation. These soft errors are particularly prevalent in memory systems. The research describes a multi-bit error detection and repair approach capable of identifying two-bit errors within a single memory row. The design proposed method is simulated and synthesized using Xilinx Verilog HDL.

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Published

2026-01-20

How to Cite

[1]
T. Vasudeva Reddy, V. Srilatha Reddy, Papani Srinivas, K. Madhava Rao, T. Prem chander, and M. S. S. Bhargav, “A Novel Diagonal Hamming technique for efficient Multi-Bit error correction in Memories”, AIJR Abs., vol. 8, no. 1, p. 78, Jan. 2026, Accessed: Jun. 13, 2026. [Online]. Available: https://abstracts.aijr.org/index.php/abs/article/view/216